This invention relates to an analog to digital converter and more particularly to technology which can be effectively applied to a successive approximation type analog to digital converter to be built in a semiconductor integrated circuit in a microcomputer or a peripheral controller.
A successive approximation type analog to digital converter (hereinafter A/D converter) built in a large scale semiconductor integrated circuit for processing data, such as a microcomputer, is comprised of a sampling circuit for an analog signal; a comparison data register for providing a quantizing level for an analog to digital conversion and a digital to analog converter circuit (hereinafter D/A converter) for providing a quantizing level for a digital to analog conversion; a comparator circuit for use in comparing the provided quantizing level with an analog signal level; and a controlling circuit for use in controlling a plurality of the above-mentioned circuits.
In the case of performing an A/D conversion, but not restricted thereto, the most significant bit in the comparison data register is initially set to "1" and all the other bits are initially set to "0". At first, a quantization level which corresponds to the most significant bit "1", i.e., half the full-scale voltage, is given from the D/A converter circuit to the comparator circuit. The comparator circuit compares the quantizing level with a voltage level of a sampled analog signal and discriminates a relationship between their values. In a case where a result of comparison is more than half of the full scale voltage, the most significant bit of the comparison data register is kept at "1". In a case where the result of comparison is less than half of the full scale voltage, the most significant bit in the comparison data register is changed to "0". In this manner, a value for the most significant bit is defined.
In performing a comparison operation for a second bit, a bit lower than the most significant bit (hereinafter second bit) in the comparison data register is set to "1" in the same manner used to determine the most significant bit. A voltage level having a load voltage of the most significant bit (a voltage level of a half of the full scale voltage) overlapped to a quantizing level corresponding to "1" of the second bit (i.e. a voltage level of 1/4 of the full scale voltage) is outputted from the D/A converter to the comparator circuit. The comparator circuit compares an output of D/A conversion with a voltage level of the an analog signal. In response to a result of comparison, a value of the second bit is defined as "1" or "0". The operation is repeated down to the least significant bit, thereby a voltage level of the sampled analog signal is converted into a corresponding digital signal and set in the comparator register as digital data.
In this way, the successive approximation type A/D converter compares the voltage level of an input analog signal with the successive quantizing level, so that its conversion action requires a predetermined time. That is, a conversion time of the successive approximation type A/D converter is longer than a conversion time of a parallel approximation type A/D converter.
Due to this fact, when the successive approximation type A/D converter is applied to convert an analog signal into a digital signal, it is not possible to perform a conversion of high accuracy without keeping the analog input signal at a constant level during its conversion period. Therefore, there is provided an A/D converter having a sample and hold function including a hold circuit for use in storing the voltage level of a sampled analog input signal during a comparison period.
An example of literature describing a single chip microcomputer having the successive approximation type A/D is disclosed in the description of Hitachi Original Single Chip Microcomputer "H8/532", page 26 published by Hitachi Ltd. in August of 1988.
The present inventor has studied the sample and hold function for the successive approximation type A/D converter, in particular the successive approximation type A/D converter built in the semiconductor integrated circuit. According to the above study, a voltage level of the analog signal must be accumulated in a stable manner in a holding capacitance.
In order to perform this operation, it is necessary to increase the holding capacitance such that noise generated on the semiconductor substrate caused by stray capacitance of a line to which an analog signal is supplied, a non-desired capacitance generated in the switching element, a disturbance in manufacturing of the element and a variation in potential of the semiconductor substrate, and the like can be substantially ignored. However, if the holding capacitance is increased, a charging time required for charging a voltage level of an analog signal to the holding capacitance is correspondingly increased. If its charging time is not sufficient, its accuracy of conversion is necessarily decreased. In turn, if its charging time is too long, an efficiency of converting operation is decreased and at the same time a level of the input analog signal having a severe variation may not be sampled accurately.
Due to these facts, a holding capacitance value of the successive approximation type A/D converter built in the semiconductor integrated circuit is set to a value within a range where the charging time is not elongated too much and where a certain high accuracy of conversion can be kept. However, the present inventor has also discovered that when performing a digital conversion of an analog input signal having a large variation, the analog input signal might be varied during a charging period for the holding capacitance, resulting in a decrease in the accuracy of conversion.
In addition, since the operation of the A/D converter is determined in response to an operating clock frequency (a system clock) for determining an operating cycle, a charging time of the analog signal with respect to the holding capacitance may also be dependent upon its operating clock frequency. Due to this fact, when the A/D's microcomputer is operated at a relatively low speed in view of its system operation, a charging time of the analog input signal with respect to the holding capacitance is relatively extended. Thus, when the voltage level of an analog input signal having a high potential variation is charged to the holding capacitance, a reduction in the accuracy of conversion of the A/D converter is made more apparent due to a variation of the voltage level of the analog input signal during its charging period.
The A/D converter having no holding function must sample an analog signal every time a comparing operation is carried out. Due to this fact, the accuracy of A/D conversion with respect to an analog input signal having a high potential variation is markedly decreased.
In view of the above fact, the present inventor studied a sample and hold circuit having a high performance at an external part in order to improve the accuracy of an A/D conversion with respect to an analog signal having a large potential variation. However, since the conventional type of A/D converter has no output means for use in outputting a sampling start timing signal, a sampling termination timing signal or a timing signal for informing its sampling period to an external part, the prior art has a problem that the above timing may not be given to the external sample and hold circuit even if a high performance sample and hold circuit is arranged at the external part. In addition, it may not be possible to efficiently inform the A/D converter as to the generation of original analog signal and due to this fact, it may not be possible to provide an easy response to a requirement for controlling its analog signal generating part.